module fifo #(
    parameter NUM_WORDS = 128,
    parameter DATA_W    = 32
) (
    input                  clk_i,
    input                  rst_i,

    // Write side
    input                  wr_i,
    input [DATA_W-1:0]     data_i,
    output                 full_o,

    // Read side
    input                  rd_i,
    output reg[DATA_W-1:0] data_o,
    output                 empty_o
);

//***********************************
// Parameters
//***********************************
localparam ADDR_WIDTH = 7;

//***********************************
// Signals
//***********************************
reg [ADDR_WIDTH-1:0] wr_addr;
reg [ADDR_WIDTH-1:0] rd_addr;
reg [NUM_WORDS-1:0] mem[DATA_W-1:0];

//***********************************
// Write side
//***********************************
always @(posedge clk_i)
  if( wr_i )
    wr_addr <= wr_addr + 1'd1;

always @(posedge clk_i)
  if( wr_i )
    mem[wr_addr] <= data_i;

//***********************************
// Read side
//***********************************
always @(posedge clk_i)
  if( rd_i )
    begin
      rd_addr <= rd_addr + 1'd1;
      data_o <= mem[rd_addr];
    end

endmodule