`timescale 1ns / 1ps

module romctrl_testbench;

reg clk_i;
reg rst_i;
reg rd_i;
reg wr_i;
reg [31:0] dat_i;
reg [4:0] adr_i;

wire [31:0] dat_o;
wire ack_o;

rom_ctrl uut (
  .clk_i(clk_i), 
  .rst_i(rst_i), 
  .rd_i(rd_i), 
  .wr_i(wr_i), 
  .dat_i(dat_i), 
  .adr_i(adr_i), 
  .dat_o(dat_o), 
  .ack_o(ack_o)
);

initial begin
  clk_i = 0;
  forever begin
    clk_i = !clk_i;
    #50;
  end
end

reg [31:0] read_value;
localparam ADR = 5'hF,
           VAL = 32'habbccdd;

	
initial begin
  rst_i = 0;
  
  clear();
  
  $display( "ROM Controller Testbench started." );
  
  $display( "Writing to ROM value 0x%h by address 0x%h...", ADR, VAL );
  write( ADR, VAL );
  $display( "Writing finished.", );

  $display( "Reading from ROM from address 0x%h...", ADR );
  read( ADR, read_value );
  $display( "Read value is 0x%h", read_value );
  
  $display( "ROM Controller Testbench finished." );

  clear();
  
  $finish();
end

task write( input [4:0] adr, input [31:0] dat );
  begin
    @( posedge clk_i );
    
    adr_i <= adr;
    dat_i <= dat;
    wr_i  <= 1;
    rd_i  <= 0;
    
    @( posedge clk_i );
    while( ack_o == 1'b1 )
      @( posedge clk_i );
      
    wr_i  <= 0;
    rd_i  <= 0;
  end
endtask

task read( input [4:0] adr, output [31:0] dat );
  begin		
    adr_i <= adr;
    wr_i  <= 0;
    rd_i  <= 1;
    
    @( posedge clk_i );
    while( ack_o == 1'b1 )
      @( posedge clk_i );
      
    dat = dat_o;		  
    wr_i  <= 0;
    rd_i  <= 0;
  end
endtask

task clear();
  begin
    @( posedge clk_i );
    rd_i <= 0;
    wr_i <= 0;
    dat_i <= 0;
    adr_i <= 0;
  end
endtask
      
endmodule